Thermal characterization of vertically stacked chips

Abstract

In this master's thesis, we review several thermal management solutions for stacked chips in portable electronics. We simulate the cooling benefits of potential thermal management solutions. Furthermore, we investigate the effect of stack layout, stacking order, and distributed power dissipation regions on the temperature.

We design a chip stack based on the design guidelines discovered in the initial investigation. Then we calculate the in-stack thermal strain induced by the temperature distribution for this stack. We conclude that proper stack design can provide considerable reduction of maximum stack temperature. While the maximum temperature of a 2 W-stack designed without consideration of thermal management can exceed 95 °C,the maximum in-stack operational temperature is below 85 °C for the stack design in the Nokia Virtual Thermal Test Environment.